Timing Gate Generator

The Timing Gate Generator uses a Red Pitaya Stemlab 125-14 to generate 8 timing channels system based on a 32 bit counter clocked at 125 MHz. The resolution of the timing system is 8nS and can have intervals as long as 17 seconds. The output of the gate generator uses the RFQ LLRF Timer Cube circuit as shown in Figure 1.

The FPGA code for the Gate Generator was developed with the Vivado 2020.2 HLS design edition following the FPGA Notes for Scientists tutorials. the overall Vivado Design view is shown in Figure 2 and a closeup of the gate design is shown in Figure 3. The design requires three custom real-time-logic (RTL) blocks

Interval counter The maximum count value of the interval counter determines the length of the gate generator interval.
Gate generator The start and stop counts of the gate generator determine the start time with respect to the interval counter and the length of the pulse.
Watchdog counter is used to verify that the gate generator is working properly and all communication links are operating.

Since the Red Pitaya Stemlab 125-14 is a Linux computer, a Blinky-Lite^TM tray can be directly installed on the Red Pitaya Stemlab 125-14. The tray code is written in the Node-RED programming environment as shown in Figure 4. The tray flow is a modified version of the standard Blinky-Lite^TM tray for serial communications. The GPIO bus of the Red-Pitay can be easily addressed with the PYNQ Python interface. A Python script using PYNQ was developed. The script is accessed though a pythonshell node labeled PYNQ Interface in dark blue as shown in Figure 4.

Figure 1. Gate Generator Implementation

Figure 2. Vivado Design view

Figure 3. Vivado Design View Closeup

Figure 4. Gate Generator Blinky-Lite^TMTray Node-RED flow